Verilog Fine-Tune: Chip Design AI on AMD MI300X

Verilog Fine-Tune is a domain-specific code generation model built for chip design. We fine-tuned Qwen 2.5 Coder 7B on the largest proprietary Verilog/VHDL/SystemVerilog corpus ever assembled — 60,000+ GitHub repos containing 444,000 clean HDL files spanning every major chip category: CPUs (RISC-V, ARM, MIPS), GPUs, TPUs, NPUs, FPGAs, ASICs, MCUs, and more. Using a single AMD Instinct MI300X with 192GB VRAM on AMD Developer Cloud, we applied LoRA fine-tuning (rank 64, alpha 128) with PyTorch and ROCm 7.0. Training completed in 4.4 hours on 50,000 sampled files at a cost of under $9, achieving a final training loss of 0.646. The fine-tuned model demonstrates clear improvements over the base model in hardware design code generation. When prompted to generate an AXI4-Lite slave interface, the base model incorrectly produces AXI4-Full burst signals, while our fine-tuned model correctly generates only AXI4-Lite channels with industry-standard conventions: active-low resets, input/output suffixes, and contextual comments noting unused signals. The model generates complete, structurally correct modules for SPI controllers, UART transceivers, synchronous FIFOs, RISC-V ALUs, and pipeline processors. Our preprocessing pipeline filters auto-generated netlists and Xilinx stubs, deduplicates by content hash, and extracts clean human-written HDL. The entire training stack runs on AMD's open-source ROCm platform with no CUDA dependency. The project is fully open-source with interactive generation and a side-by-side comparison demo showing base vs fine-tuned output quality.