"Puul team on AMD Developer Hackathon Hackathon"

Team Idea

AI chip design copilot fine-tuned on 444K Verilog files. Generates production-quality RTL on AMD MI300X.

Team Members

Wheezy Salem

wheezy

Submission

Verilog Fine-Tune: Chip Design AI on AMD MI300X

Fine-tuned Qwen 2.5 Coder 7B on a proprietary Verilog/VHDL/SystemVerilog corpus for chip design code generation. Built at the AMD Developer Hackathon SF (May 9-10, 2026).