VLSI Verification Co-Pilot

The VLSI Verification Co-Pilot is an advanced AI agent designed to revolutionize hardware engineering workflows by accelerating Verilog synthesis optimization and testbench verification. Hardware verification is traditionally one of the most time-consuming bottlenecks in chip design. Subtle race conditions in testbenches or unintended latches in RTL can cost engineering teams weeks of debugging. To solve this, we built an AI-powered verification assistant fine-tuned specifically for the VLSI domain. At the core of the project is the state-of-the-art Qwen 3.5 (9B) reasoning architecture, which we successfully fine-tuned using custom Verilog datasets. By leveraging the immense compute power and memory bandwidth of the AMD Instinct MI300X cloud instance, we were able to run Supervised Fine-Tuning (SFT) and merge LoRA adapters to create a highly specialized logic synthesis model. The backend runs on a high-performance FastAPI server directly on the AMD Developer Cloud, providing rapid inference. On the frontend, we engineered a cinematic, modern React application that parses the model's 'Chain of Thought' reasoning in real-time. This allows hardware engineers to understand exactly how the AI identified potential race conditions or synthesis inefficiencies before applying the optimized code. Built entirely on the AMD ROCm ecosystem, this project demonstrates how open-source foundation models can be fine-tuned on AMD hardware to automate and secure the future of semiconductor design.