Arihant Bansal@darkhacker

CUDA is locked to NVIDIA hardware, forcing custom hardware teams (RISC-V GPUs, FPGAs, and research accelerators) to reinvent their compiler stacks from scratch. Worse, they lack a reference model to verify parallel correctness, leading to undetected data races on new silicon. POLYFORGE solves this by decoupling the surface language from the hardware backend using a revolutionary AI-assisted pipeline. It uses Fireworks AI (Kimi-2.6) to comprehend and extract a structured IR from standard CUDA kernels. Because LLMs can hallucinate, POLYFORGE never trusts the AI blindly. Instead, it passes the extracted IR through a custom Zero-Trust Parallel Oracle. This oracle independently simulates thread execution to prove the absence of Read-After-Write (RAW), Write-After-Write (WAW), and Write-After-Read (WAR) data races. Once mathematically verified, the hardware abstraction layer automatically lowers the safe kernel into C++ tailored for the target hardware. In our implementation for the AMD Developer Hackathon ACT II, POLYFORGE compiles standard CUDA code directly onto a simulated Vortex RISC-V GPU, executing successfully on the SIMX hardware simulator. POLYFORGE ensures that you write CUDA once, verify it mathematically, and run it on ANY parallel architecture. Today, it targets Vortex. Tomorrow, it can target anything.

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