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RTL Repair
RTL Repair is a fine-tuned Verilog/SystemVerilog repair assistant built for common RTL bugs. The user provides a design intent and buggy RTL code, and the model returns fixed RTL, a short explanation of the bug, and a verification suggestion. The project focuses on beginner/intermediate hardware design issues such as FSM transition mistakes, reset bugs, blocking vs non-blocking assignment problems, counter boundary errors, and incomplete combinational logic. I started by evaluating Qwen2.5-Coder-7B-Instruct as a baseline, then built a curated RTL repair dataset and fine-tuned the model using LoRA. One important failure mode came from tick-driven FSMs. Earlier versions incorrectly changed transitions to use `!tick`, even when the design intent clearly said that `tick` should advance the FSM. I added targeted contrast examples, retrained the model, and fixed that behavior in the demo. The project includes a Gradio demo, Hugging Face Space landing page, uploaded LoRA adapter, manual score summaries, Icarus Verilog compile checks, behavioral simulations, and a one-command project check runner. I also reproduced the training and evaluation workflow on AMD Developer Cloud using ROCm-compatible tooling.
10 May 2026
